In general, field programmable arrays, further referred to herein and abbreviated as FPGA, are used to implement some computing functionality which is intended to run basic, hardware related functions used to control the basic functions of computer periphery, which recognizes video screens, printers, network cards, etc.
Further, FPGAs are used in applications which require a vast amount of basic arithmetic computations, e.g., multiplication and addition operations, that have to be performed very quickly in graphic processing applications.
FPGAs are used to implement computational functionality which is implemented in a large number (up to 1 million) of inter-connected circuits. Such vast cicuits are planned and realized with the help of a special hardware, e.g., the hardware device of Byte BlasterMV, which is connected to either the serial or the parallel port of the workstation used in turn as a development platform with dedicated software tools.
This is depicted in FIG. 2, where a PCI card is shown schematically connected to extra hardware 32 external to the PC. Logic 34 is provided for controlling and programming the FPGA 16 with the configuration data to be developed for the FPGA and feeding it with the configuration data necessary for the PCI card to be detected by the bus system on a system start-up. Such prior art development environments require either additional hardware or Programmable Read Only Memory devices, further referred to herein as PROMs. The developed schema containing the new functionality is fed into the PROM which is placed onto the PC-card to be developed comprising the FPGA. After a subsequent POWER-On of the developer's workstation, the PROM controls and performs the configuration of the FPGA. Then, the functionality of the FPGA can be tested during operation. If a further update of the schema is necessary, a new PROM has to be used, as the used one can not be rewritten.
Alternatively, Electrical Erasable PROMs, further referred to herein as EEPROMS are used instead of PROMs. They can be rewritten in case of a further update, however, external hardware is necessary in order to control the write process into the EEPROM.
During development of FPGA functionality, or when an end-user exchanges a PC-card comprising said FPGA due to any update or extension of functionality incorporated in his card, manual access to the concerned card is necessary. In the case of a FPGA developer, manual access is needed to replace at least the PROM used to program the FPGA. In the latter instance, manual access to the concerned card is necessary in order to replace the card by another. The same basically applies when instead of an update, any new functionality is implemented on an FPGA.
Any manual access to PC-cards, however, causes additional work and bears the risk to damage other hardware connected in the casing of the computer, e.g., by statical charges brought to any of a plurality of locations sensitive thereto.